Ivris Raymond

Author: Ivris Raymond | Major: Computer Engineering | Semester: Fall 2022

I’m Ivris Raymond, a Computer Engineering major in the College of Engineering. My mentor is Dr. Alex Nelson of the CSCE department. I conducted the research discussed in this post throughout the Spring 2022 and Fall 2022 terms, and am planning to continue this research through at least the Spring 2023 term. I graduate Spring 2023, and this research will likely continue until then.

My project has grown a bit more interesting since my last blog post, as I’ve changed the topic of my project. Originally, I was working on using Bluetooth Angle of Arrival to detect distracted driving, but I switched at the beginning of the Fall 2022 semester to processing in memory for FPGA devices.

Firstly, I’ll touch on how things were going with the original project. Due to the equipment not operating in the required frequencies, I had to improvise with my phone and some Bluetooth beacons in the lab. However, this wasn’t with Angle of Arrival, as I would need multiple phones (ideally at least 3) in order to have enough antennas to do the triangulation of the device’s exact position in three dimensions. Given the sensitivity of just the one antenna, though, I believe it would be possible to design a device capable of triangulating the position of a phone in a form factor suiting an OBDII device. More testing should be done to confirm this for future work, though.

As for my new project, the problem it seeks to solve is in the load-store operations required anytime we want to perform a computation. Instead of just being able to add two numbers together, you first have to go retrieve those values from memory, then add them, and finally you store the result for later use. The idea with processing in-memory is to remove those load and store operations by moving the processing element inside of the memory, and memristive devices are one way to enable this functionality.

Currently, I’m working on learning the tools required to design the fabric of an FPGA that uses memristive devices for some of the blocks that are capable of implementing logic. With these tools, my current theory is that I can break up the current design of the memory for the SPAR-2 array processor into tiles and implement certain portions with memristive elements. From there my current plan is to include the processing element in the memory blocks to allow the SPAR-2 array processor to be mapped to a processing in-memory implementation.

Finally, this project would have been much more difficult to spend time on and acquire materials for without the Honors College Research Grant. The support of the grant allowed me to acquire the materials needed to conduct the experiments for this research so far, and it will continue to be important going into the Spring 2023 term. Without the support of the Honors College I likely wouldn’t have gotten as far as I did on this research.

As I mentioned earlier, I plan to continue pursuing this research in the Spring 2023 term. This research has also helped me discover my interests for graduate school, and I intend to continue pursuing research related to this topic if possible in graduate school.